Charge-Trap (CT) Non-Volatile Memory (NVM) typically stores quantities of electrical charge that are representative of data values in an isolating layer, such as a nitride layer. Drifting of the stored charge may degrade the memory performance. Several techniques are known in the art for reducing drift effects in NVM.
For example, U.S. Pat. No. 8,593,884, whose disclosure is incorporated herein by reference, describes a data retention method that includes sampling a plurality of non-volatile memory devices included in a data storage device to detect retention information for each of the nonvolatile memory devices in response to a request of a host. Sampling data is output from the data storage device to the host based on a result of the sampling. The host determines whether to perform a retention operation on each of the non-volatile memory devices based on the sampling data, and performing the retention operation on each of the nonvolatile memory devices based on a result of the determination.
As another example, U.S. Pat. No. 8,446,778, whose disclosure is incorporated herein by reference, describes a Charge-Trap Flash memory device that is capable of preventing data retention fail by ensuring a data retention margin. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Data retention states of the selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.